Like the I2C protocol, the Serial Peripheral Interface, or SPI, was built to replace parallel bus lines with a serial interface, but can operate at way higher speeds, because there's no addressing overhead involved when devices are selected and it may also transfer info in both directions at the same time. Understanding SPI may be necessary for your next microcontroller project!
Unlike I2C, there may be only one device configured as a master, while each one of the other devices are configured as slaves. The basic operation is composed of shifting information out of the master into one of the slaves, while at the same time shifting information into the master from the selected slave. This is rather like having 2 8-bit shift registers set up in a "ring" fashion, but any arbitrary number of bits may be transferred.
The master selects a slave with by using outputs configured as "slave selects" (SS1, SS2, and so on). These SS lines are normally high, and then one of them is set low to enable the selected slave device on its CS (chip select) pin. This pin is configured to be a high impedance input on each of the slaves so it wouldn't meddle when other chips are selected. There are three other lines needed for this to work. The master clocks the serial info out and in utilizing its SCLK clock output pin, which is hooked up to the SCLK inputs on each one of the slaves. The master receives data from the slaves through its SDI (serial data input) pin, which connects to the SDO (serial data output) pin on every one of the slaves. The master sends information with its SDO pin, which connects to the SDI pins on the slaves. All 4 I/O lines on the slaves are kept at a high impedance level at every point, except for the SDO pin on a slave even though it is selected, when it changes its state to an output briefly to transmit data.
A data transference would begin with the master selecting one of the slaves by setting its CS line low. Understanding the clocking of the transfer now becomes terribly tricky, depending on how 2 parameters called clock polarity (CPOL) and clock phase (CPHA) are defined, which sets the edges of the clock signal that the data is changed and then sampled. These settings are determined in advance - the information sheet for each module will show you which modes it supports.
As soon as CS is lowered, and when CPHA = 0, the 1st bit is transferred on the clock's next edge, which is rising or falling, depending on whether CPOL is low or high. Then the data would change state on the subsequent clock edge (rising or falling), and the cycle would repeat itself until the master makes a decision to end the transfer by setting CS back to high.
When CPHA = one, the timing phase changes so that the information changes state on the first clock edge after CS is decreased, which is either rising or falling, again dependent on CPOL. The first bit would then be transferred on the subsequent clock edge, and this process continues till the transfer is complete.
Unlike I2C, there may be only one device configured as a master, while each one of the other devices are configured as slaves. The basic operation is composed of shifting information out of the master into one of the slaves, while at the same time shifting information into the master from the selected slave. This is rather like having 2 8-bit shift registers set up in a "ring" fashion, but any arbitrary number of bits may be transferred.
The master selects a slave with by using outputs configured as "slave selects" (SS1, SS2, and so on). These SS lines are normally high, and then one of them is set low to enable the selected slave device on its CS (chip select) pin. This pin is configured to be a high impedance input on each of the slaves so it wouldn't meddle when other chips are selected. There are three other lines needed for this to work. The master clocks the serial info out and in utilizing its SCLK clock output pin, which is hooked up to the SCLK inputs on each one of the slaves. The master receives data from the slaves through its SDI (serial data input) pin, which connects to the SDO (serial data output) pin on every one of the slaves. The master sends information with its SDO pin, which connects to the SDI pins on the slaves. All 4 I/O lines on the slaves are kept at a high impedance level at every point, except for the SDO pin on a slave even though it is selected, when it changes its state to an output briefly to transmit data.
A data transference would begin with the master selecting one of the slaves by setting its CS line low. Understanding the clocking of the transfer now becomes terribly tricky, depending on how 2 parameters called clock polarity (CPOL) and clock phase (CPHA) are defined, which sets the edges of the clock signal that the data is changed and then sampled. These settings are determined in advance - the information sheet for each module will show you which modes it supports.
As soon as CS is lowered, and when CPHA = 0, the 1st bit is transferred on the clock's next edge, which is rising or falling, depending on whether CPOL is low or high. Then the data would change state on the subsequent clock edge (rising or falling), and the cycle would repeat itself until the master makes a decision to end the transfer by setting CS back to high.
When CPHA = one, the timing phase changes so that the information changes state on the first clock edge after CS is decreased, which is either rising or falling, again dependent on CPOL. The first bit would then be transferred on the subsequent clock edge, and this process continues till the transfer is complete.
About the Author:
Embedded Adventures is a great website for exploring microcontroller projects, and finding modules that use SPI and I2C to communicate, like an alphanumeric led display or a real time clock.
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